The present invention relates generally to power semiconductor devices, and more specifically to techniques for driving the gate of large power devices such as power MOSFETs and insulated gate bipolar transistors (IGBTs).
The operation of a power MOS device entails rapid charging and discharging of the gate to cause transitions through the device's linear region between its fully enhanced (“on”) and fully shut off (“off”) states. Typical gate drive circuit technology applies a DC voltage to the device gate to charge and discharge the gate and thus change the device state. This gate voltage is chosen to be above the full enhancement voltage but below the maximum gate voltage. Reference to the gate voltage or voltage on the gate is normally the voltage relative the source (if the device is an FET), or relative to the emitter (if the device is an IGBT).
The power dissipation of the device is reasonably given by the product of drain-source current and drain-source voltage. When the device is in its off state, the drain-source voltage is significant, but there is substantially no drain-source current, and the dissipation is extremely low. Similarly, when the device is in its on state, the drain-source current is significant, but the drain-source voltage is substantially zero, and the dissipation is extremely low. However, when the device is passing through its linear state, the drain-source current is increasing/decreasing and drain-source voltage is decreasing/increasing (depending on the direction of the transition). During this time, power is being dissipated.
Thus, it is a well-known goal to improve the switching speed, but like many well-known goals, it is easier the than done. The ability to rapidly charge and discharge the gate is impeded by a number of factors, including one or more of the following: (a) inductance and resistance introduced by the package and system interconnect; (b) the Miller effect (the tendency of a capacitance to be multiplied by the gain of adjacent stages in a electrical circuit); and (c) source and drain inductance.
For a given voltage applied to the gate drive point of the device to be switched, the speed at which the gate voltage can change is limited by the complex impedance, including offsets, of the circuit, even if the gate driver has zero impedance. However, using a larger steady-state drive voltage to overcome the complex impedance of the switching system and increase the switching speed would destroy the device being switched as soon as the charge on the gate exceeded the maximum allowable charge for the device.